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dual 8-,10-,12-bit, high bandwidth multiplying dacs with parallel interface ad5428/ad5440/ad5447 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 10 mhz multiplying bandwidt h fast paralle l in terface (58 msps write cycle) ad75 28 upgrade (a d54 28) ad75 47 upgrade (a d54 47) 2.5 v to 5.5 v s u pply operation 10 v refer e nce input 20- an d 24 -lea d tssop packa g es dual 8-, 10-, an d 12-bit curren t output d a cs guarantee d m o notonic 4-qua d rant m u ltiplication power-on reset readback func tion 0.5 a t y pical c u rrent consumption func ti on a l bl ock di a g r a m 04462- 0- 001 control logic input buffer data inputs i out a db0 dac a/b cs r/w dgnd db7 db9 db11 i out b agnd ad5428/ad5440/ad5447 latch latch 8-/10-/12-bit r-2r dac a 8-/10-/12-bit r-2r dac b power-on reset v dd v ref a v ref b r fb a r fb b r r f i g u re 1. a d 54 28 /a d54 4 0 /a d 5 4 47 applic a t io ns portable batter y -powered applications waveform gen e rators analog processing instrumentation applications programmable amplifiers and attenuators digitall y controlled calibratio n programmable filters and osci llators composite video ultrasound gain, offset, an d voltage trim ming gener a l description the ad5428/ad5440/ad5447 1 a r e d u al cm os 8-, 10-, a nd 12-b i t c u r r en t ou t p ut dig i t a l- t o - a na log co n v er t e rs (d a c s), re sp e c t i vely . th es e de vices op era t e f r o m a 2. 5 v t o 5.5 v p o w e r s u p p l y , ma k i ng t h e m su i t e d to b a tte r y - p owe r e d a n d ot he r a p pl i c a t i o ns . the d a c s u t i l i z e da t a r e ad b a ck, al lo win g t h e us er t o r e ad t h e co n t e n ts o f t h e d a c r e g i s t er v i a t h e d b p i n s . on p o w e r - up , t h e in t e r n al r e g i st er a nd l a t c h e s a r e f i l l e d wi th zer o s a nd t h e d a c output s are at z e ro s c a l e. a s a re su lt of man u f a c t u r e on a c m o s submic ron p r o c e s s , t h e y o f f e r e x ce l l en t 4-q u adra n t m u l t i p lica tion c h a r ac t e r i s t ics, wi th l a rge s i g n a l m u lt i p ly ing b a ndwi d t hs of u p to 1 0 m h z. the a p plie d exter n al r e fer e n c e i n p u t v o l t a g e ( v ref) deter m i n es t h e f u l l -s cale o u t p u t c u r r en t. a n in teg r a t e d fe e d b a ck r e sis t o r (r fb ) p r o v ides tem p er a t ur e t r ackin g and f u l l -s c a le v o l t a g e o u t p u t w h en com b in e d wi t h a n ext e r n al i-t o -v p r ecisio n a m plif ier . the ad5428 is a v a i la b l e in a s m al l 20-lead t s so p p a c k a g e , while t h e ad54 40/ad5447 d a cs a r e a v a i lab l e in smal l 24-lead t sso p p a c k a g es. 1 us patent number 5,689,257.
ad5428/ad5440/ad5447 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 te r m i no l o g y .................................................................................... 10 typical performance characteristics ........................................... 11 general description ................................................................... 16 circuit operation ....................................................................... 16 single-supply applications ........................................................ 18 positive output voltage ............................................................. 19 adding gain ................................................................................ 19 used as a divider or programmable gain element ............... 19 reference selection .................................................................... 20 amplifier selection .................................................................... 20 parallel interface ......................................................................... 20 microprocessor interfacing ....................................................... 20 pcb layout and power supply decoupling ........................... 21 evaluation board for the dacs ................................................ 21 power supplies for the evaluation board ................................ 21 bill of materials ............................................................................... 25 overview of ad54xx devices ....................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 28 revision history 7/04revision 0: initial version
ad5428/ad5440/ad5447 rev. 0 | page 3 of 28 specifications temperature range for y version is C40c to +125c. v dd = 2.5 v to 5.5 v, v ref a = v ref b = +10 v, agnd = 0 v. all specifications t min to t max , unless otherwise noted. dc performance measured with op1177, ac performance with ad8038, unless otherwise noted. table 1. parameter min typ max unit conditions static performance ad5428 resolution 8 bits relative accuracy 0.25 lsb differential nonlinearity 1 lsb guaranteed monotonic ad5440 resolution 10 bits relative accuracy 0.5 lsb differential nonlinearity 1 lsb guaranteed monotonic ad5447 resolution 12 bits relative accuracy 1 lsb differential nonlinearity C1 /+2 lsb guaranteed monotonic gain error 10 m v gain error temp coefficientt 1 5 ppm fsr/c output leakage current 10 na data = 0000 h , t a = 25c. 25 na data = 0000 h. reference input 1 reference input range 10 v v ref a, v ref b input resistance 8 10 12 k ? input resistance tc = C50 ppm/c v ref a to v ref b input resistance mismatch 1.6 2.5 % typ = 25c, max = 125c r fb a,r fb b input resistance 8 10 12 k ? input resistance tc = C50 ppm/c input capacitance code 0 3 6 pf code 4095 5 8 pf digital inputs/output 1 input high voltage, v ih 1.7 v v dd = 2.5 v to 5.5 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v input leakage current, i il 2 a input capacitance 4 10 pf v dd = 4.5 v to 5.5 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd ? 1 v i source = 200 a v dd = 2.5 v to 3.6 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd ? 0.5 v i source = 200 a dynamic performance 1 reference multiplying bw 10 mhz v ref = 3.5 v, dac loaded all 1s output voltage settling time v ref = 10 v, r load = 100 ?, c load = 15 pf dac latch alternati vely loaded with 0s and 1s ad5428 30 60 ns measured to 16 mv of fs ad5440 35 70 ns measured to 4 mv of fs ad5447 80 120 ns measured to 1 mv of fs
ad5428/ad5440/ad5447 rev. 0 | page 4 of 28 parameter min typ max unit conditions digital delay 20 40 ns interface delay time 10% to 90% settling time 15 30 ns rise and fall time, v ref = 10 v, r load = 100 ? digital-to-analog glitch impulse 2 nv -s 1 lsb change around major carry, v ref = 0 v multiplying feedthrough error C75 db dac latches loaded with all 0s. reference = 10 khz output capacitance i out 2 22 25 pf dac latches loaded with all 0s 10 12 pf dac latches loaded with all 1s i out 1 12 17 pf dac latches loaded with all 0s 25 30 pf dac latches loaded with all 1s digital feedthrough 1 nv ? s feedthrough to dac output with cs high and alternate loading of all 0s and all 1s total harmonic distortion ? 81 db v ref = 3.5 v p-p, all 1s loaded, f = 1 khz output noise spec tral density 25 nv/hz @ 1 khz sfdr performance (wideband) ad5447, 65 k codes, v ref = 3.5 v clock = 10 mhz 500 khz f out 55 db 100 khz f out 63 db 50 khz f out 65 db clock = 25 mhz 500 khz f out 50 db 100 khz f out 60 db 50 khz f out 62 db sfdr performance (narrow band) ad5447, 65 k codes, v ref = 3.5 v clock = 10 mhz 500 khz f out 73 db 100 khz f out 80 db 50k hz f out 87 db clock = 25 mhz 500 khz f out 70 db 100 khz f out 75 db 50 khz f out 80 db intermodulation distortion ad5447, 65 k codes, v ref = 3.5 v clock = 10 mhz f 1 = 400 khz, f 2 = 500 khz 65 db f 1 = 40 khz, f 2 = 50 khz 72 db clock = 25 mhz f 1 = 400 khz, f 2 = 500 khz 51 db f 1 = 40 khz, f 2 = 50 khz 65 db power requirements power supply range 2.5 5.5 v i dd 0.6 a t a = 25c. logic inputs = 0 v or v dd 0.5 10 a logic inputs = 0 v or v dd power supply sensitivity 1 0.001 %/% ?v dd = 5% 1 guaranteed by design, not subject to production test.
ad5428/ad5440/ad 5447 rev. 0 | page 5 of 2 8 timing characteristics t e m p er a t ur e ran g e f o r y v e rsio n is C40c t o +125c. g u a r a n te ed b y desig n and c h a r ac t e r i za tio n , n o t s u b j ec t to p r o d uc tio n t e s t . al l in p u t sig n als a r e s p ecif ie d wi t h tr = tf = 1 n s (10% t o 90% o f v dd ) and t i me d f r om a vol t age l e vel of ( v il + v ih )/2. digi t a l o u t p u t timin g m e as ur e d wi th lo ad c i r c ui t in f i gur e 3. v dd = 2.5 v t o 5.5 v , v ref = 10 v , i ou t 2 = 0 v . a l l sp e c if ic a t ion s t min to t max , u n le ss ot he r w i s e note d . table 2. parameter limit at t min , t ma x unit conditions/comments write mode t 1 0 ns min r/ w to cs setup tim e t 2 0 ns min r/ w to cs hold time t 3 10 ns min cs low time t 4 10 ns min address setup ti me t 5 0 ns min address hold time t 6 6 ns min data setup time t 7 0 ns min data hold time t 8 5 ns min r/ w high to cs low t 9 7 ns min cs min high time data readback mode t 10 0 ns typ address setup ti me t 11 0 ns typ address hold time t 12 5 ns typ data access time 25 ns max t 13 5 ns typ bus relin q uish time 10 ns max 04462-0-002 data valid data valid data daca/dac b cs r/w t 1 t 3 t 4 t 10 t 5 t 8 t 7 t 11 t 9 t 2 t 8 t 2 t 12 t 13 f i g u re 2. ti ming d i ag r a m 04462-0-003 to output pin v oh (min) + v ol (max) 200 ai oh 200 ai ol 2 c l 50pf f i gure 3 . l o a d cir c ui t fo r d a ta o u tput t i m i ng sp eci f i c a t io ns
ad5428/ad5440/ad 5447 rev. 0 | page 6 of 2 8 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g v dd to gnd C0.3 v to +7 v v ref a, v ref b, r fb a, r fb b to dgnd C12 v to +12 v i ou t 1, i ou t 2 to dg nd C0.3 v to +7 v logic inputs and output 1 C0.3 v to v dd + 0.3 v operating tem p erature range automotive (y v e rsion) C40c to +125c storage temperature range C65c to +150c junction tempe r ature 150c 20-lead tssop ja thermal impe dance 143c/w 24-lead tssop ja thermal impe dance 128c/w lead temperature, soldering ( 10 second s) 300c ir reflow, peak temperature ( < 20 second s) 235c 1 o v er v o lt ages a t dbx, cs , and w /r a r e c l a m ped b y i n t e rn a l di ode s . c u rr en t s h ould be l imit ed t o the maximum ratings giv e n. s t r e s s es a b o v e t h os e lis t e d i n a b s o l u t e m a xi m u m r a t i n g s ma y ca us e p e r m a n e n t da ma g e t o t h e de vic e . this is a s t r e s s ra t i n g on ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or an y ot he r co ndi t i on s ab o v e t h os e list e d in t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t ion is n o t i m plie d . e x p o sur e t o a b s o lu t e maxi m u m r a t i n g condi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vic e r e liab i l i t y . on ly o n e abs o l u te m a xim u m r a t i ng ma y b e a p pli e d at a n y o n e t i m e . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5428/ad5440/ad 5447 rev. 0 | page 7 of 2 8 pin conf igurations and f u ncti on descriptions 04462-0-004 r/w cs 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 i out a r fb a v ref a db7 dac a/ b dgnd agnd r fb b v ref b v dd db0 (lsb) db4 db5 db6 db3 db2 db1 i out b ad5428 top view (not to scale) f i gure 4. pin config ur ation 20-l ead t s sop (ru-20) ta ble 4. a d 54 28 pi n f u nct i o n d e s c ri pt i o ns pin no. mnemonic function 1 agnd dac ground pin . typically, this pin should be tied to the analog ground of the system, but may be bias ed to achieve single- s upply operatio n . 2, 20 i ou t a, i ou t b dac current ou tputs. 3, 19 r fb a, r fb b dac feedback resistor pins. establ ish voltage output for the d a c by conne cting to ex ternal amplifier output. 4, 18 v ref a, v ref b dac reference voltage input terminal s. 5 dgnd digital ground pin. 6 dac a/b selects dac a or b. low sele cts da c a, or, alternatively, high se lects dac b. 7 to14 db7 to db0 paralle l data bit s 7 through 0. 15 cs chip select inpu t. active low. used in conjunction with r/ w to load parallel data to the input latch or to read data from the d a c register. 16 r/ w read/ w rite. when low, used in conj unction wit h cs to load paral l e l d a ta. when hi gh, used in conj unction with cs to read back contents of t h e dac register. 17 v dd positive power s u pply input. this part can be o p e rated from a supply of 2.5 v to 5.5 v.
ad5428/ad5440/ad 5447 rev. 0 | page 8 of 2 8 04462-0-005 r/w cs 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 i out a r fb a v ref a db9 dac a/b dgnd agnd r fb b v ref b v dd nc db8 db7 db4 db5 db6 nc db0 (lsb) db3 db2 db1 i out b ad5440 top view (not to scale) nc = no connect f i gure 5. pin config ur ation 24-l ead t s sop (ru-24) ta ble 5. a d 54 40 pi n f u nct i o n d e s c ri pt i o ns pin no. mnemonic function 1 agnd dac ground pin. t y pically, this pin shou ld be tied to the analog ground of the system, but may be biased to achieve single- s upply operatio n . 2, 24 i ou t a, i ou t b dac current ou tputs. 3, 23 r fb a, r fb b dac feedback resistor pins. establ ish voltage output for the d a c by conne cting to ex ternal amplifier output. 4, 22 v ref a, v ref b dac reference voltage input terminal s. 5 dgnd digital ground ppin. 6 dac a/b selects dac a or b. low sele cts da c a, or, alternatively, high se lects dac b. 7 to16 db9 to db0 paralle l data bit s 9 through 0. 19 cs chip select inpu t. active low. us ed in conjunctio n with r/ w to loa d paralle l d a ta to the input latch or to read data from the d a c register. 20 r/ w read/ w rite. when low, used in conj unction wit h cs to load paral l e l d a ta. when hi gh, used in conjunction with cs to read back contents of the dac register. 21 v dd positive power s u pply input. this part can be o p e rated from a supply of 2.5 v to 5.5 v.
ad5428/ad5440/ad 5447 rev. 0 | page 9 of 2 8 04462-0-006 r/w cs 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 i out a r fb a v ref a db11 dac a/b dgnd agnd r fb b v ref b v dd db0 (lsb) db10 db9 db6 db7 db8 db1 db2 db5 db4 db3 i out b ad5447 top view (not to scale) f i gure 6. pin config ur ation 24-l ead t s sop (ru-24) ta ble 6. a d 54 47 pi n f u nct i o n d e s c ri pt i o ns pin no. mnemonic function 1 agnd dac ground pin. t y pically, this pin shou ld be tied to the analog ground of the system, but may be biased to achieve single- s upply operatio n . 2, 24 i ou t a, i ou t b dac current ou tputs. 3, 23 r fb a, r fb b dac feedback resistor pins. establ ish voltage output for the d a c by conne cting to ex ternal amplifier output. 4, 22 v ref a, v ref b dac reference voltage input terminal s. 5 dgnd digital ground pin. 6 dac a/b selects dac a or b. low sele cts da c a, or, alternatively, high se lects dac b. 7 to 18 db11 to db0 paralle l data bit s 11 through 0. 19 cs chip select inpu t. active low. us ed in conjunctio n with r/ w to loa d paralle l d a ta to the input latch or to read data from the d a c register. when cs and r/ w are held low, the latc hes are trans p ar ent; any change s on the d a ta lines wi ll b e reflected on the relevant dac output. 20 r/ w read/ w rite. when low, used in conj unction wit h cs to load paral l e l d a ta. when hi gh, used in conjunction with cs to read back contents of dac register. when cs an d r/ w are held lo w, the latches a r e transpare n t; any changes on the d a ta lines are re fl ected on the relevant dac output. 21 v dd positive power s u pply input. this part can be o p e rated from a supply of 2.5 v to 5.5 v.
ad5428/ad5440/ad 5447 rev. 0 | page 10 of 28 terminology re l a ti ve a c c u r a c y rela t i v e acc u rac y o r en d p oin t n o nl inea r i ty is a m e as ur e o f th e maxim u m d e v i a t io n f r o m a st r a ig h t li ne p a ssing t h r o ug h t h e e n d p oi n t s of t h e d a c t r ans f e r f u nc t i o n . i t i s m e a s u r e d af te r ad j u st ing fo r ze r o a n d f u l l s c a l e a nd is ty p i ca l l y ex p r ess e d i n ls bs o r as a p e r c en t a g e o f f u l l -s cale r e adin g. d i f f erenti a l n o n l i n e a r i ty dif f er en t i al n o n l in e a r i ty is t h e dif f er en ce b e twe e n t h e m e as ur e d cha n ge and t h e ide a l 1 ls b chan ge b e twe e n an y tw o ad jace n t co des. a sp e c if i e d dif f er en t i a l no n l i n e a r i ty o f ? 1 ls b max o v er t h e o p era t i n g t e m p er a t ur e ra n g e en s u r e s m o n o t o nici ty . ga in er r o r ga in er r o r o r f u l l -s cale er r o r is a me as ur e o f t h e o u t p ut er r o r bet w een a n i d eal d a c a n d t h e act u al de v i ce o u t p u t . f o r th e s e d a cs, ide a l ma x i m u m o u t p ut i s v ref C 1 ls b . ga in er r o r o f t h e d a cs is ad j u s t ab le t o zer o wi t h ext e r n al r e sis t a n ce. ou t p u t l e akage c u rr e n t o u t p u t le a k a g e c u r r en t f l o w s in t h e d a c ladde r swi t ch es w h e n t h es e a r e t u r n e d o f f. f o r t h e i ou t 1 t e r m inal , i t can b e m e as ur e d b y lo adin g a l l 0s t o t h e d a c and m e asur in g t h e i ou t 1 c u r r en t. mini m u m c u r r en t f l o w s in t h e i ou t 2 lin e w h en t h e d a c is lo ade d wi th al l 1s. ou t p u t c a pacita n c e ca pa c i t a n c e fr o m i ou t 1 o r i ou t 2 t o a g nd . o u tp u t c u r r e n t s e tt l i n g ti m e this is t h e am oun t o f tim e i t ta k e s f o r th e o u t p u t t o s e t t le t o a s p e c if ie d le ve l f o r a f u l l -s cale in p u t c h a n ge . f o r th es e de vices, i t is s p ecif ie d wi t h a 100 ? r e sis t o r t o g r o u n d . dig i ta l-t o -anal o g glit ch lmpu ls e the am o u n t o f c h a r g e in jec t e d f r o m th e dig i ta l in p u ts t o the a n alog o u t p u t w h en the in p u ts cha n g e s t a t e . this is n o r m al l y s p eci f i e d a s t h e a r ea o f th e gli t ch i n ei t h e r pa -s ecs o r n v -secs dep e n d in g up on w h et h e r t h e g l i t ch is m e asur e d as a c u r r en t or vol t age s i g n a l . dig i ta l f e e d thr o ug h w h en t h e de vic e is n o t s e lec t ed , hig h f r eq uen c y log i c ac ti vi ty o n th e de v i ce d i gi t a l i n p u t s i s ca paci ti v e l y co u p le d th r o ugh th e d e v i c e to show up a s noi s e on t h e i ou t p i ns and subs e q u e n t ly in t o t h e fol l o w i n g cir c ui t r y . this n o is e is dig i t a l fe e d t h r o ug h. m u l t iply in g f e e d thr o ug h e rro r this is t h e er r o r d u e t o c a p a ci t i v e fe e d t h r o ug h f r o m t h e d a c re f e re nc e i n put to t h e d a c i ou t 1 t e rm i n al , w h en all 0s a r e lo ade d t o the d a c. t o t a l ha r m on i c d i s t or t i on ( t h d ) the d a c is dr i v en b y a n ac r e fer e n c e . the ra t i o o f t h e r m s s u m o f th e h a rm o n i c s o f th e d a c o u t p u t t o th e fun d a m en tal v a l u e i s t h e t h d . u s u a l l y on ly t h e l o we r - ord e r h a r m on i c s are i n clu d e d , s u c h as s e con d to f i f t h. ( ) 1 2 5 2 4 2 3 2 2 log 20 v v v v v thd + + + = dig i ta l i n t e rm o d u l a t i o n dist o r ti o n se c o n d - o r d e r i n t e rm od ul a t i o n d i s t o r t i o n ( i m d ) m e a s u r e m e n t s a r e t h e r e la t i v e ma g n i t ude o f t h e fa an d f b t o n e s g e n e r a t e d dig i t a l l y b y t h e d a c and t h e s e co nd-o r der p r o d uc ts a t 2fa ? ff b a nd 2fb ? fa . s p uri o us-f r e e d y na mi c r a n g e (s fd r) s f d r is th e us ab le d y namic ra ng e o f a d a c bef o r e s p ur io us n o is e in t e r f er es o r dis t o r ts t h e f u ndam e n t al sig n al . s f d r is t h e m e as ur e o f dif f er en ce in am pli t ude b e tw e e n t h e f u ndam e n t al a nd t h e la rgest ha r m o n i c a l ly - o r n o n h a r m o ni c a l l y - r e la te d sp u r f r o m dc t o f u l l n y q u is t bandwid th (half the d a c s a m p lin g ra t e , or f s / 2 ) . n a r r ow - b a n d sf dr i s a me a s u r e of sf dr ove r an a r b i tra r y win d o w si ze , i n th i s case 50% , o f th e f u n d a m e n t al . dig i t a l s f d r is a me as ur e o f t h e us a b le d y nami c ra n g e o f t h e d a c w h e n t h e sig n a l is dig i t a l l y gen e r a te d si ne wa ve.
ad5428/ad5440/ad 5447 rev. 0 | page 11 of 28 typical perf orm ance cha r acte ristics ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 inl ( l sb) 0.10 0.15 0.20 04462-0-007 0 5 0 100 150 200 250 code t a = 25c v ref = 10v v dd = 5v f i gure 7. inl vs . code (8-b it d a c ) ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 inl ( l sb) 04462-0-008 0 200 400 600 800 1000 code t a = 25c v ref = 10v v dd = 5v f i g u re 8. inl v s . co de (1 0-bit da c ) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl ( l sb) 2000 1 500 500 1000 0 2500 300 0 3 5 0 0 4000 code 04462-0-009 t a = 25c v ref = 10v v dd = 5v f i g u re 9. inl v s . co de (1 2-bit da c ) ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 dnl (ls b ) 0.10 0.15 0.20 04462-0-010 0 5 0 100 150 200 250 code t a = 25c v ref = 10v v dd = 5v f i gure 10. dnl vs . c o de ( 8 -bit d a c ) ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (ls b ) 04462-0-011 0 200 400 600 800 1000 code t a = 25c v ref = 10v v dd = 5v f i g u re 11. dnl v s . code ( 10-b i t da c ) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 dnl (ls b ) 2000 1 500 500 1000 0 2500 300 0 3 5 0 0 4000 code 04462-0-012 t a = 25c v ref = 10v v dd = 5v f i g u re 12. dnl v s . code ( 12-b i t da c )
ad5428/ad5440/ad 5447 rev. 0 | page 12 of 28 ? 0.3 ? 0.2 ? 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 inl ( l sb) 6 5 34 2 789 1 0 reference voltage 04462-0-013 max inl min inl t a = 25c v ref = 10v v dd = 5v f i gure 13. inl v s . r e ferenc e v o ltage ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 dnl (ls b ) 6 5 34 27 8 9 reference voltage 04462-0-014 1 0 min dnl t a = 25c v ref = 10v v dd = 5v f i gure 14. dnl v s . r e fer e n c e v o lt age ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 e rror (mv ) ?60 ? 40 ?20 0 20 40 60 80 100 120 140 temperature ( c) 04462-0-015 v dd = 5v v dd = 2.5v v ref = 10v f i gure 15. g a in e r ror v s . t e mper atur e input voltage (v) curre nt (ma) 8 5 0 5.0 7 6 3 1 4 2 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 2 5 c v dd = 5v v dd = 3v v dd = 2.5v 04462-0-022 f i gure 16. sup p l y current v s . l o gic i n p u t v o ltag e 0 0.2 0.4 0.6 0.8 1.0 i out le akage (na) 1.2 1.4 1.6 40 20 ?2 0 0 ?40 60 80 1 0 0 1 2 0 temperature (c) 04462-0-023 i out 1 v dd 5v i out 1 v dd 3v f i g u re 17. i ou t 1 l e a k ag e cu rrent v s . t e mpe r at u r e 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 curre nt ( a) ?60 ? 40 ?20 0 20 40 60 80 100 120 140 temperature ( c) 04462-0-024 t a = 25c v dd = 5v v dd = 2.5v all 0s all 1s all 0s all 1s f i gure 18. sup p l y current v s . t e mper at ur e
ad5428/ad5440/ad 5447 rev. 0 | page 13 of 28 0 2 4 6 8 10 12 14 i dd (ma) 10 k 1k 1 0 100 1 100k 1m 10 m 100 m frequency (hz) 04462-0-025 t a = 25c loading zs to fs v dd = 5v v dd = 3v v dd = 2.5v f i gure 19. sup p l y current v s . u p date r a te ? 102 ?66 ?54 ?42 ?30 ?18 ?6 6 1 100 1k 10k 100k 1m 10m 100m frequency (hz) gain ( d b) t a = 25 c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25 c v dd = 5v v ref = 3.5v input c comp =1 . 8 p f ad8038 amplifier all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off 04462-0-026 10 f i gure 20. reference mult iplying b a nd width vs. f r equenc y and code ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 gain ( d b) 10k 1k 10 100 1 1 0 0 k 1 m 10m 1 00m frequency (hz) 04462-0-027 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier f i g u re 21. r e f e rence m u lt iply i n g b a nd widt hCa ll o n es l o aded ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequency (hz) t a = 25c v dd = 5v gain ( d b) 04462-0-028 v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf f i gure 22. reference mult iplying b a nd width vs. f r equenc y and comp en s a t i on cap a c i to r ?0.010 ?0.005 0.005 0.025 0.035 0.045 0.015 0 0.020 0.030 0.040 0.010 output voltage (v) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 time (ns) 04462-0-041 t a = 25c v ref = 0v ad8038 amplifier c comp = 1.8pf 7ff to 800h 800 to 7ffh v dd = 5v v dd = 3v v dd = 3v v dd = 5v f i g u re 23. m i ds c a l e t r ans i t i on, v ref = 0 v output voltage (v) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 time (ns) 04462-0-042 ?1.77 ?1.76 ?1.75 ?1.74 ?1.73 ?1.72 ?1.71 ?1.70 ?1.69 ?1.68 7ff to 800h 800 to 7ffh v dd = 5v v dd = 3v v dd = 3v v dd = 5v t a = 25c v ref = 3.5v ad8038 amplifier c comp = 1.8pf f i g u re 24. m i ds c a l e t r ans i t i on, v ref = 3 . 5 v
ad5428/ad5440/ad 5447 rev. 0 | page 14 of 28 ? 120 ? 100 ?80 ?60 0 20 1 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr ( d b) 04462-0-043 10 f i gure 25. p o wer s u p p ly rej e c t ion vs. f r equ e nc y ?90 ?85 ?80 ?75 ?70 ?65 ?60 thd + n (db) 100 1k 1 1 0 10k 100k 1m frequency (hz) 04462-0-044 t a = 25c v dd = 3v v ref = 3.5v p-p fi g u r e 2 6 . t h d + n o i s e v s . fr e q u e n c y 0 20 40 60 80 100 s f dr (db) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 f out (khz) 04462-0-045 t a = 25c v ref = 3.5v ad8038 amplifier mclk = 1mhz mclk = 200khz mclk = 0.5mhz f i g u re 27. wideb a n d sfdr v s . f ou t fre q u e n c y 0 10 20 30 40 50 60 70 80 90 sfd r ( d b ) 0 100 200 300 400 500 600 700 800 900 1000 f out (khz) 04462-0-046 mclk = 5mhz mclk = 10mhz mclk = 25mhz t a = 25c v ref = 3.5v ad8038 amplifier f i g u re 28. wideb a n d sfdr v s . f ou t fre q u e n c y 04462-0-047 ?9 0 ?7 0 ?5 0 ?3 0 ?1 0 s f dr (db) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 2 4 6 8 10 12 f i g u re 29. wideb a n d sfdr , f ou t = 1 00 k h z, c l o c k = 2 5 m h z 044620-048 ?100 ?7 0 ?5 0 ?3 0 ?1 0 s f dr (db) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 ?9 0 f i g u re 30. wideb a n d sfdr , f ou t = 5 00 k h z, c l o c k = 1 0 m h z
ad5428/ad5440/ad 5447 rev. 0 | page 15 of 28 04462-0-049 ?9 0 ?7 0 ?5 0 ?3 0 ?1 0 s f dr (db) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 t a = 25 c v dd = 5v amp = ad8038 65k codes f i g u re 31. wideb a n d sfdr , f ou t = 5 0 k h z, c l o c k = 1 0 m h z 04462-0-050 frequency (mhz) t a = 25 c v dd = 3v amp = ad8038 65k codes ?100 ?7 0 ?5 0 ?3 0 ?1 0 sfd r ( d b ) 250 750 300 350 400 650 700 ?8 0 ?6 0 ?4 0 ?2 0 0 ?9 0 450 500 550 600 f i gure 32. na rro w - band spec tr al r e s p ons e , f ou t = 5 00 k h z, cl ock = 25 m h z 04462-0-051 ?120 ?6 0 ?2 0 s f dr (db) 50 150 frequency (mhz) 60 70 80 130 140 ?8 0 ?4 0 0 20 ?100 90 100 110 120 t a = 25 c v dd = 3v amp = ad8038 65k codes f i gure 33. na rro w - band sf dr , f ou t = 1 00 k h z, c l ock = 2 5 mh z 04462-0-052 frequency (mhz) ?100 ?7 0 ?5 0 ?3 0 ?1 0 (db) 70 120 75 80 85 115 ?8 0 ?6 0 ?4 0 ?2 0 0 ?9 0 90 100 105 110 t a = 25 c v dd = 3v amp = ad8038 65k codes 95 f i gure 34. na rro w - band imd , f ou t = 90 kh z, 10 0 k h z, c l oc k = 1 0 m h z 04462-0-053 ? 100 ?40 ?20 (db) ?50 ?30 ?10 ?90 ?60 ?70 ?80 0 400 frequency (khz) 50 300 350 100 150 200 250 0 t a = 25 c v dd = 5v amp = ad8038 65k codes f i g u re 35. wideb a n d im d , f ou t = 90 kh z, 1 0 0 kh z , cl ock = 25 m h z 100 1k 10k 100k frequency (hz) t a = 25 c amp = ad8038 full scale loaded to dac zero scale loaded to dac 04462-0-054 0 50 100 150 200 250 300 outp ut nois e (nv / hz) midscale loaded to dac f i g u re 36. o u t p ut nois e spe c t r a l d e n s it y
ad5428/ad5440/ad 5447 rev. 0 | page 16 of 28 general description circuit o p eratio n unipola r mo de the ad5428, ad5440 a nd ad5447 a r e d u al 8 - , 10- a nd 12-b i t c u r r en t o u t p u t d a cs co n s ist i ng o f a st anda r d i n ver t in g r - 2r ladder co nf igur a t io n. a sim p l i f i e d d i a g r a m fo r t h e 8- b i t ad5428 is sh o w n in f i gur e 37. the f eedbac k resis t o r r fb has a val u e o f r . th e val u e o f r is typical l y 10 k? (mi n im u m 8 k? a nd max i m u m 12 k?). i f i out 1 a nd i ou t 2 a r e k e p t a t t h e s a m e p o t e n t ia l , a co n s ta n t c u r r en t f l o w s in e a ch ladder leg, r e ga r d les s of d i g i t a l i n pu t c o d e . t h e r e f ore, t h e i n pu t re s i s t anc e pre s e n te d at v ref is a l w a y s co n s t a n t and no mina l l y o f va l u e r . t h e d a c output ( i ou t ) is co de de p e n d e n t, p r o d ucin g va r i o u s r e sis t a n ces a nd c a p a ci t a n c e s . e x t e r n a l a m plif ier ch o i ce sh ou ld t a k e i n t o acco un t t h e v a r i a t io n in i m p e dan c e ge ner a te d b y t h e d a c on t h e am plif ier s i n v e r t in g i n p u t n o d e . u s in g a sin g le op a m p , th e s e de vices c a n e a sil y be co nf igur e d to prov i d e 2 - q u a d r a n t m u lt iply i n g op e r a t i o n or a u n ip o l ar output v o l t a g e s w in g, as s h own in f i gu r e 38. w h en a n o u t p u t a m p l if ier is co nne c t e d i n uni p ol a r m o de, t h e o u t p ut vol t age is g i ven b y n ref out d v v 2 / ? = w h er e d is t h e f r ac t i o n al r e p r es en t a t i o n o f t h e dig i t a l w o r d lo ade d to t h e d a c a nd n i s t h e re s o lut i on of t h e d a c . d = 0 t o 255 (8-b i t ad5428) = 0 t o 1023 (1 0-b i t ad5440) = 0 t o 4095 (1 2-b i t ad5447) 04462-0-029 v ref dac data latches and drivers r fb a i out 1 i out 2 rr r r 2r 2r 2r 2r 2r s1 s2 s3 s8 n o t e tha t t h e ou t p u t v o l t a g e p o la r i ty is o p p o si t e t o the v ref p o la r i ty fo r dc r e fer e n c e v o l t a g e s . th es e d a cs ar e desig n e d t o o p era t e w i t h e i t h er n e g a t i v e o r p o si t i v e r e fer e nce v o l t a g es. the vd d p o w e r p i n is o n l y us ed b y th e in t e r n al dig i tal log i c t o dr i v e t h e o n and o f f s t a t es o f t h e d a c s w i t ch es . t h ese d a c s a r e al so d e s i gn e d t o a cco mm o d a t e a c r e f e r e n c e in p u t sig n als in th e ra n g e o f C10 v t o +10 v . f i gure 37. si mpl i fi e d ladde r w i t h a f i x e d 1 0 v re f e re nc e, t h e c i rc u i t i n fi g u re 8 g i ve s a uni p ol a r 0 v t o C10 v o u t p u t v o l t a g e s w ing. w h en v in is an ac sig n al , th e cir c u i t p e r f o r m s 2-q u adran t m u l t i p l i ca tion. a c cess is p r o v id e d t o t h e v ref , r fb , a nd i ou t te r m i n a l s of d a c a a nd d a c b , ma kin g t h e de vice ext r em e l y v e rs a t i l e a nd al lo wi ng i t t o b e co nf igure d i n s e v e ral dif f er en t o p era t in g m o des, fo r e x am pl e, to prov i d e a u n i p ol ar out p ut , 4 - qu a d r a n t m u lt i p l i c a - t i on i n bip o l a r mo d e or i n s i ng l e - s upply mo d e s of op e r a t i o n . n o t e tha t a ma tc hin g s w i t ch is us ed in s e r i es wi th t h e in t e r n al r fb fe e d b a ck r e s i st o r . i f us ers a t tem p t t o m e asure r fb , p o w e r mu s t b e ap p l i e d t o v dd to a c h i e v e c o n t i n u i t y . the fol l o w in g t a b l e sh o w s t h e r e l a t i o n shi p b e t w e e n dig i t a l co de and t h e exp e c t e d o u t p u t vol t a g e fo r uni p ola r o p era t ion (ad5428, 8-b i t de vice). table 7. unip o l ar code table digital input analog output (v) 1111 1111 Cv ref (255/256) 1000 0000 Cv ref (128/256) = Cv ref /2 0000 0001 Cv ref (1/256) 0000 0000 Cv ref (0/256) = 0
ad5428/ad5440/ad 5447 rev. 0 | page 17 of 28 04462-0-030 control logic input buffer data inputs i out a db0 dac a/b cs r/w dgnd db7 db9 db11 i out b agnd ad5428/ad5440/ad5447 latch latch agnd 8-/10-/12-bit r-2r dac a 8-/10-/12-bit r-2r dac b power-on reset v dd v ref a v in a (10v) v ref b r fb a r fb b r r v out a r1 1 v in b ( 10v) r3 1 r2 1 c1 2 agnd v out b r4 1 c2 2 1 2 r1, r2 and r3, r4 used only if gain adjustment is required. c1, c2 phase compensation (1pf ?2pf) is required when using high speed amplifiers to prevent ringing or oscillation. notes: f i g u re 38. u n ipol ar o p er at io n bipolar operation i n s o me a p pl i c a t i o ns , i t m a y b e ne c e ss ar y to ge ne r a te f u l l 4 - qu a d r a n t m u lt i p ly ing op e r a t i o n or a bi p o l a r ou t p ut s w ing . this can be easi l y acco m p lish e d b y usin g a n o t her ext e r n al a m plif ier an d s o m e ext e r n a l r e sist o r s, as sh ow n in f i gur e 39. i n t h is cir c ui t, t h e s e con d am pl if ier , a2, p r o v ides a ga in o f 2. biasin g t h e exte r n al a m plif ier w i t h an o f fs et f r o m t h e r e fer e n c e v o lt ag e re s u lt s i n f u l l 4 - qu a d r a n t m u lt ip l y i n g o p e r a t i o n . t h e tra n sf e r fun c ti o n o f th i s ci r c ui t s h o w s tha t bo th n e ga ti v e a n d p o si t i v e o u t p ut v o l t a g es a r e cr e a t e d as t h e i n p u t da t a (d) is i n cr em en t e d f r o m cod e z e r o (v ou t = ? v ref ) t o midscale (v ou t = 0 v) t o f u l l s c ale (v ou t = +v ref ). w h e n co nne c t e d in b i p o la r m o de , t h e o u t p ut v o l t a g e is g i v e n b y ( ) ? = ? 1 2 / w h er e d is t h e f r ac t i o n al r e p r es en t a t i o n o f t h e dig i t a l w o r d lo aded t o the d a c, a nd n is t h e n u m b er o f b i ts. d = 0 t o 255 (ad5428) = 0 t o 1023 (ad5440) = 0 t o 4095 (ad5447) wh e n v in is a n ac sig n al , th e circ ui t p e r f o r m s 4-q u adra n t m u lt ipl i c a t i on . t a bl e 8 s h ow s t h e re l a t i onsh ip b e t w e e n d i g i t a l co de and t h e ex p e c t e d o u t p u t vol t a g e fo r b i p o lar o p er a t io n (ad5428, 8-b i t de vice). table 8. bipola r code tabl e digital input analog output (v) 1111 1111 +v ref (127/128) 1000 0000 0 0000 0001 Cv ref (127/128) 0000 0000 Cv ref (128/128) stability i n th e i - t o - v c o n f i g u r a t i o n , th e i o u t o f th e d a c a n d th e in ver t ing no de o f t h e o p a m p m u st b e co n n e c te d a s clo s e as p o s s i b le and p r o p er pcb l a yo u t t e chniq u es m u s t b e em plo y e d . b e ca us e e v er y co de cha n ge co r r es p o n d s t o a s t e p f u n c t i o n , ga i n p e akin g ma y o c c u r if t h e o p a m p has limi t e d g b p an d t h er e is exces s i v e p a rasi t i c ca p a c i t a n c e a t t h e i n v e r t in g n o de . this p a rasi t i c c a p a ci t a n c e in t r o d uces a p o le in t o t h e o p en lo o p r e sp o n s e w h ich ca n ca us e r i n g i n g o r in st ab i l i t y in t h e clos e d l o o p ap p l i c at i o n s c i r c u i t . an o p t i o n a l com p e n s a t i on c a p a ci to r , c1, ca n b e adde d i n pa r a ll e l w i th r fb fo r st a b i l i t y , as sh own i n f i gur e 38 a nd in f i gur e 39. t o o smal l a val u e o f c1 can p r o d uce r i n g in g a t t h e o u t p ut, w h i l e t o o la rg e a val u e c a n ad vers e l y a f fe c t t h e s e t t l i n g time . c1 sh o u ld be f o und em p i r i cal l y , b u t 1 pf to2 pf is g e n e rall y ad e q ua t e f o r the co m p en s a tio n .
ad5428/ad5440/ad 5447 rev. 0 | page 18 of 28 04462-0-031 control logic input buffer data inputs i out a db0 dac a/b cs r/w dgnd db7 db9 db11 i out b agnd ad5428/ad5440/ad5447 latch latch agnd 8-/10-/12-bit r-2r dac a 8-/10-/12-bit r-2r dac b power-on reset v dd v ref a v in a (10v) v ref b r fb a r fb b r rr 2 1 v out a r1 1 v in b (10v) r3 1 r6 2 20k ? r5 20k ? r8 20k ? r11 5k ? r12 5k ? r7 2 10k ? r9 2 10k ? r10 2 20k ? c1 2 agnd agnd agnd v out b r4 1 c2 2 a1 a3 a2 a4 1 2 3 r1, r2 and r3, r4 used only if gain adjustment is required. adjust r1 for v out a = 0v with code 10000000 in dac a latch. adjust r3 for v out b = 0v with code 10000000 in dac b latch. matching and tracking is essential for resistor pairs r6, r7 and r9, r10. c1, c2 phase compensation (1pf ?2pf) may be required if a1/a3 is a high speed amplifier. notes: f i g u re 39. bipol a r o p er at ion ( 4 - q uad r ant m u lt ip li c a t i on ) single-sup ply a pplic atio ns voltage-swit ching mode f i gur e 40 s h o w s t h es e d a cs o p era t in g in v o l t ag e-s w i t chi n g mo d e . t h e re f e re nc e vo lt ag e, v in , is a p plie d t o t h e i ou t 1 p i n, i ou t 2 is co nn e c te d to a g nd , and t h e o u tp u t volt a g e is a v a i la b l e at t h e v ref t e r m ina l . i n t h is con f igura t io n, a p o s i t i v e r e fer e n c e vol t age re su l t s i n a p o s i t i ve output vol t ag e, ma k i ng s i ng l e - su p p ly op e r a t ion p o ss ibl e . t h e ou t p ut f r om t h e d a c is vol t ag e a t co nst a n t i m p e dan c e (t he d a c ladder r e sist an ce), t h us an o p a m p is n e cess a r y t o b u f f er t h e o u t p ut v o l t a g e. th e r e fer e n c e i n put no l o nge r s e e s c o nst a n t i n put i m p e d a nc e, b u t o n e t h a t va r i es wi t h co de. s o , t h e v o l t a g e in p u t sh o u ld b e dr i v en f r o m a lo w im p e dan c e s o ur ce . no t e t h a t v in is limi te d t o lo w vol t a g es b e c a us e t h e s w i t ch es i n t h e d a c ladder n o lo n g er ha ve t h e s a me s o ur ce -dra i n dr i v e vol t a g e. a s a r e su l t , t h eir on r e sist an ce dif f ers a nd t h is deg r ade s th e in t e gral lin e a r i t y o f th e d a c . also , v in mu s t n o t g o n e g a t i v e b y m o r e tha n 0. 3 v o r a n in t e r n al dio d e t u r n s on, exceedin g t h e m a xi m u m ra tin g s o f th e d e v i ce . i n th i s t y pe o f a p p l i c a t i o n , t h e full ra n g e o f m u l t i p l y i n g ca pa b i li t y o f th e d a c is l o s t . 04462-0-033 1 2 additional pins omitted for clarity. c1 phase compensation (1pf ?2pf) may be required if a1 is a high speed amplifier. notes: v dd v in v ref v dd r fb gnd v out i out 1 i out 2 r 1 r 2 f i gure 40. sing le-s up ply v o ltag e-s w itching m o de
ad5428/ad5440/ad 5447 rev. 0 | page 19 of 28 posi tive o u tput voltage n o te t h e out p ut volt age p o l a r i t y i s opp o s i te to t h e v ref po la ri t y for dc re fe re nc e vol t age s . f o r a p o s i t i ve vol t ag e out p ut , an a p plie d n e g a t i v e r e fer e n c e t o t h e in p u t o f t h e d a c is p r efer r e d o v er t h e o u t p u t in v e rsion t h r o ug h a n i n v e r t in g a m plif ier b e ca us e o f t h e resis t o r s t o lera nce er r o rs. t o g e n e ra t e a nega t i ve re f e re nc e, t h e re f e re nc e c a n b e l e vel sh i f t e d by a n op am p su ch th a t t h e v ou t a nd gnd p i n s o f t h e r e fer e nce b e c o m e t h e vir t ual g r ou nd a n d C 2 . 5 v re sp e c t i vely , a s s h ow n i n fi g u re 4 1 . 04462-0-034 1 2 additional pins omitted for clarity. c1 phase compensation (1pf ? 2pf) may be required if a1 is a high speed amplifier. notes: v dd = +5v v dd c 1 v in v ref r fb 8-/10-/12-bit dac adr03 1/2 ad8552 1/2 ad8552 gnd gnd v out v out = 0v to 2.5v i out 1 i out 2 +5v ?5v ?2.5v f i g u r e 4 1 . p o s i ti v e v o l t a g e ou t p u t w i th mi ni m u m c o m p o n e n t s adding g a in i n a p plic a t io n s w h er e t h e o u t p u t v o l t a g e is r e quir e d t o b e gr ea t e r th a n v in , ga in can b e ad de d w i t h an o t h e r ex ter n a l a m p l if ier o r i t c a n als o b e ac hie v ed in a sing le sta g e . i t is im p o r t an t t o t a k e i n t o con s ider a t io n t h e ef fe c t o f t e m p er a t ur e co ef f i cien ts o f t h e t h in f i lm r e si s t o r s o f t h e d a c. sim p l y placi n g a r e sis t o r in s e r i es wi t h t h e r fb r e sis t o r ca us es misma t ch es in t h e t e m p era t ur e co ef f i cien ts, r e s u l t in g i n la rg er ga i n t e m p er a t ur e co ef f i cien t er r o rs. i n s t e a d , t h e ci r c ui t o f f i gur e 42 s h o w s t h e r e co mmen d e d m e t h o d o f in cr e a sin g t h e ga in of th e cir c ui t. r 1 , r 2 , a nd r 3 sh o u l d al l ha ve simi lar t e m p er a t ur e c o ef f i cien ts, b u t t h e y n e e d n o t ma t c h t h e t e m p era t ur e co ef f i cie n ts o f t h e d a c. this a p p r o a c h is r e co mmen d e d in cir c ui ts w h ere ga in s o f >1 are re qu i r e d . 04462-0-035 1 2 additional pins omitted for clarity. c1 phase compensation (1pf ? 2pf) may be required if a1 is a high speed amplifier. notes: v dd v dd c 1 v in v ref r fb r 2 r 3 r 2 8-/10-/12-bit dac gnd v out i out 1 i out 2 r 2 + r 3 r 2 gain = r 1 = r 2 r 3 r 2 + r 3 f i gure 42. inc r e a sin g g a in of cu rrent o u tput d a c used as a divider or programm able gain element c u r r en t-st e e r i ng d a cs a r e v e r y f l exi b le a n d le nd t h e m s e l v es to ma n y d i f f er en t a p plic a t ion s . i f t h is ty p e o f d a c is co nne c t e d as th e f e e d ba ck e l em en t o f a n o p a m p a n d r fb is us e d as t h e in p u t re s i stor a s sho w n i n fi g u re 4 3 , t h e n t h e output vo lt age i s i n v e r s e l y p r o p o r ti o n al t o th e digi tal in p u t f r a c tio n d . fo r d = 1-2 n th e o u t p u t v o l t a g e i s () 2 1 / / ? ? = ? = v out v dd gnd v in i out 2 i out 1 r fb v dd v ref note: a dditional pins omitted for clarit y 04462-0-040 f i gure 43. cur r ent- stee ring d a c used as a d i v i d e r or p r og r a m m ab le g a i n e l e m ent a s d is r e d u ce d, t h e o u t p u t v o l t a g e i n cr e a s e s. f o r smal l val u es o f th e d i g i tal f r acti o n d , i t i s im po r t a n t t o en s u r e th a t t h e a m plif ier do es n o t s a t u ra te an d a l s o t h a t t h e r e q u ir e d acc u rac y is m e t. f o r ex a m ple, a n 8 - b i t d a c dr i v en wi t h t h e b i na r y co de 0 10 (0001000 0)tha t is, 16 decimalin the cir c ui t o f f i gur e 43 s h o u l d c a us e t h e o u t p u t v o l t a g e t o b e 16 v in . h o w e v e r , if t h e d a c has a li n e ar i t y sp e c if ic a t ion o f 0.5 ls b , th en d can, in f a c t , ha v e t h e weig h t an y w h e r e in the ra n g e 15.5/256 t o 16.5 / 256 s o tha t t h e p o s s i b le o u t p u t v o l t a g e is in t h e ra n g e 15.5 v in to 16.5 v in a n e r r o r o f 3% ev en th o u g h t h e d a c i t s e lf has a max i m u m er r o r o f 0.2%. d a c le a k a ge c u r r en t is a l s o a p o t e n t ia l er r o r s o ur ce in d i vi der cir c ui ts. th e le a k a g e c u r r en t m u s t b e co u n t e rb alan ce d b y a n opp o s i te c u r r e n t suppl i e d f r om t h e op a m p t h ro u g h t h e d a c . b e c a u s e on ly a f r a c t i on , d , of t h e c u r r e n t i n to t h e v ref te r m i n a l is r o u t e d t o t h e i ou t 1 t e r m inal , th e o u t p u t v o l t a g e m u s t c h an g e to : o u t p ut e r ror v o lt ag e d u e t o d a c l e ak ag e ( ) / = w h er e r is t h e d a c r e sis t an ce a t t h e vref ter minal. f o r a d a c leaka g e c u r r en t o f 10 na, r = 10 k ? and a ga i n (i .e, a/ d) o f 16, t h e er r o r v o l t a g e is 1.6 mv .
ad5428/ad5440/ad 5447 rev. 0 | page 20 of 28 reference selection w h en s e le c t in g a r e fer e n c e fo r us e wi t h t h e ad 54x x s e r i es o f c u r r en t o u t p u t d a cs, p a y a t t e n t io n t o t h e r e fer e n c e s o u t p ut v o l t a g e t e m p era t ur e co ef f i cien t s p e c if ic a t ion. this p a ra m e t e r n o t only a f fe c t s t h e f u l l -s cale er r o r , b u t ca n als o a f fe c t t h e l i ne ar it y ( i n l a n d dn l ) p e r f or m a n c e. t h e re f e re nc e t e m p era t ur e co ef f i cien t sh o u ld b e con s is t e n t wi t h t h e sys t e m acc u rac y sp e c if ica t ion s . f o r exa m ple , a n 8 - b i t s y st em r e q u ir e d t o h o ld i t s o v era l l sp e c if ic a t ion to wi t h in 1 l s b o v er t h e t e m p era t ur e ra ng e 0 t o 50c di c t a t es t h a t t h e maxim u m sys t e m dr if t w i t h tem p e ra t u r e sh o u ld b e les s t h an 78 p p m /c. a 12 -b i t sys t em w i t h t h e s a me t e m p er a t u r e ra n g e t o o v eral l s p e c if ic a t ion wi t h in 2 ls bs re q u ir es a maxi m u m dr if t o f 10 p p m / c. by cho o s i ng a pre c i s i o n re f e re nc e w i t h l o w output te m p e r atu r e co ef f i cien t t h is er r o r s o ur ce ca n b e mi nimize d. t a b l e 9 lists s o m e of t h e re f e re nc e s a v ai l a bl e f rom a n a l o g d e v i c e s , inc . t h a t a r e s u i t ab le fo r us e wi t h t h is ran g e o f c u r r en t o u t p ut d a cs. amplifier selection the p r ima r y r e q u ir em e n t fo r t h e c u r r en t- s t e e r i n g m o de is a n a m plif ier wi t h lo w in p u t b i as c u r r en ts a nd lo w in p u t o f fs et volt age. t h e i n put of f s e t volt age of an op am p i s m u lt i p l i e d b y th e v a r i a b le g a in (d ue t o t h e co d e - d epen d e n t o u t p u t r e s i s t a n ce o f t h e d a c) o f t h e cir c ui t. a cha n g e i n t h e n o is e ga in b e tw e e n tw o ad jacen t di g i t a l f r ac t i o n s pr o d uces a st ep cha n g e i n t h e o u t p ut v o l t a g e d u e t o t h e am plif ier s in p u t o f fs et v o l t a g e . thi s o u t p u t v o l t a g e cha n g e is s u p e r i m p os e d o n t h e c h a n g e in o u t p u t b e tw e e n t h e t w o co des a nd g i ves r i s e to a dif f er en t i a l l i ne a r i t y er r o r , w h ich if to o la rg e mig h t c a us e t h e d a c to b e n o nm on o- t o nic. th e i n p u t o f fs et v o l t a g e sh o u ld b e <1/4 l s b t o en s u r e mo noto n i c b e h a v i or w h e n ste p pi ng t h rou g h c o d e s . the i n p u t b i as c u r r en t o f a n o p a m p als o g e nera t e s a n o f fs et a t t h e v o l t a g e o u t p u t as a r e s u l t o f t h e b i as c u r r en t f l o w in g in t h e f eed ba ck r e s i s t o r , r fb . m o s t o p a m ps ha ve in p u t b i as c u r r en ts lo w en o u g h t o pr e v en t sig n if ican t er r o rs in 12- b i t a p pli c a t io n s . i n v o l t a g e-swi t chin g cir c ui ts, co mm on-mo d e r e jec t io n o f t h e op a m p is i m p o r t an t b e c a us e i t p r o d uces a c o de- d ep e n de n t er r o r a t t h e v o l t a g e o u t p u t o f t h e cir c ui t. m o s t o p a m ps ha v e ade q u a te c o m m o n - m o d e r e j e c t i o n f o r u s e at 8-, 10-, a n d 1 2 -b i t r e s o l u tio n . p r o v ide d t h e d a c sw i t ch es a r e dr i v en f r o m t r ue wideb a n d , lo w im p e d a n c e s o urces (v in and a g nd), they s e t t le q u ic kl y . th us, th e s l ew ra t e a n d set t li n g tim e o f a v o l t a g e - sw i t ch i n g d a c c i rc u i t i s d e te r m i n e d l a r g ely by t h e output op am p . t o o b t a i n mini m u m s e t t li n g t i m e i n t h is c o nf igura t io n, i t is im p o r t an t t o m i n i m i z e ca pa ci ta n c e a t th e v re f no de ( v ol t a ge o u t p ut no de i n t h is a p plic a t ion ) o f t h e d a c. this is do ne b y usin g lo w in p u t ca p a c i t a n c e b u f f er a m plif iers a nd ca r e f u l b o a r d desig n . m o st s i ng l e - s upply c i rc u i t s i n c l u d e g rou nd a s p a r t of t h e an a l o g sig n a l ra n g e , w h ich in t u r n s r e quir es a n am plif ier t h a t can h a n d le ra il-t o-ra il sign als. an alog devices, i n c. p r o v id es a la r g e var i ety of s i ng l e -su p ply am pl if iers . parallel interf ace da t a is lo aded to th e ad5428/ ad5440/ ad54 47 in t h e f o r m a t of an 8 - , 1 0 - , or 1 2 - bit p a r a l l el w ord. c o n t ro l l i n e s cs a nd r/ w a l l o w da t a to b e w r i tte n to or re ad f rom t h e d a c re g i ste r . a wr i t e e v e n t t a k e s place w h en cs a nd r/ w a r e b r o u g h t lo w , da t a a v a i la b l e on t h e da t a li n e s f i l l s t h e shif t r e g i st er , a nd t h e r i sin g ed g e o f c s la t c h e s th e da ta a n d tra n s f e r s th e la t c h e d d a ta w o r d t o t h e d a c r e g i s t er . the d a c l a t c h e s a r e n o t t r a n s p a r en t, t h us a wr i t e s e q u en ce m u s t co n s ist o f a fal l in g and r i sin g edg e on cs to en s u r e da t a is lo ade d t o t h e d a c r e g i s t er an d i t s a n alog eq ui v a len t r e f l ect e d o n th e d a c o u t p u t . a r e ad e v en t t a k e s pl ace w h e n r/ w is h e ld hig h and cs is b r o u g h t lo w . d a t a is lo ade d f r o m t h e d a c r e g i s t er b a ck t o t h e in p u t r e g i s t er and o u t on t o t h e da t a li ne w h er e i t can b e r e ad b a ck to t h e c o n t ro l l e r f o r ve r i f i ca t i on or d i ag no st i c pu r p o s e s . the i n p u t and d a c r e g i s t ers of t h es e de vices ar e n o t t r ansp are n t , s o a f a l l i n g a n d r i s i ng e d ge of cs is r e q u ir e d t o lo ad ea c h d a ta -w o r d . microprocessor interfacing the ad5428/ad5440/ad5447 ca n be in ter faced t o a va r i ety o f 16-bi t micr o c on t r ol lers o r ds p p r o c ess o rs. f i gur e 44 sh o w s t h e ad54xx d a c in t e r f ace d t o a gen e r i c 16-b i t micr o c o n tr ol ler/ d s p pro c e s s o r . mi c ropro c e ss or i n te r f a c i n g to t h i s f a m i ly of d a cs is vi a a d a t a b u s t h a t us es st anda r d p r o t o c ol co m p a t i b l e wi t h micr o c on t r ol lers a n d ds p p r o c ess o rs. the addr ess de c o de r is us ed t o s e lec t d a c a o r d a c b a nd als o t o lo ad p a ral l e l da t a to t h e i n put l a tc h or to re a d d a t a f rom t h e d a c u s i n g an a n d g a te. ad54xx* dac a/b cs wr db0 to db11 a0 to ax micro/dsp* wr db0 to db11 a address decoder data bus address bus a + 1 04462-0-055 *additional pins omitted for clarity f i g u re 44. a d 5 4 x x t o p a r a ll el inte r f ace
ad5428/ad5440/ad5447 rev. 0 | page 21 of 28 pcb layout and power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5428/ad5440/ad5447 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd- to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. these dacs should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the soldered side. it is good practice to employ compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize on high frequency performance, the i-to-v amplifier should be located as close to the device as possible. evaluation board for the dacs the evaluation board consists of a dac and a current to voltage amplifier ad8065. included on the evaluation board is a 10 v reference, adr01. an external reference may also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software simply allows the user to write a code to the device. power supplies for the evaluation board the board requires 12 v, and +5 v supplies. the +12 v v dd and vss are used to power the output amplifier, while the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors. table 9. suitable adi precision references recommended for use wi th ad5428/ad5440/ad5447 dacs reference output voltage initial tolerance tem perature drift 0.1 hz to 10 hz noise package adr01 10 v 0.1% 3 ppm/c 20 v p-p sc70, tsot, soic adr02 5 v 0.1% 3 ppm/c 10 v p-p sc70, tsot, soic adr03 2.5 v 0.2% 3 ppm/c 10 v p-p sc70, tsot, soic adr425 5 v 0.04% 3 ppm/c 3.4 v p-p msop, soic table 10. precision adi op amps suit able for use with ad5428/ad5440/ad5447 dacs part # max supply voltage v v os (max) vi b (max) na i b (max) na gbp mhz slew rate v/s op97 20 25 0.1 0.9 0.2 op1177 18 60 2 1.3 0.7 ad8551 +6 5 0.05 1.5 0.4 table 11. high speed adi op amps suitable for use with ad5428/ad5440/ad5447 dacs part # max supply voltage v bw @ a cl mhz slew rate v/s v os (max) v i b (max) na ad8065 12 145 180 1500 0.01 ad8021 12 200 100 1000 1000 ad8038 5 350 425 3000 0.75
ad5428/ad5440/ad 5447 rev. 0 | page 22 of 28 04464-0-023 v dd v ss u3 c7 1. 8pf j1 7 4 3 2 6 v? v+ + c11 10 f c9 10 f c12 0. 1 f c8 0. 1 f c3 10 f c14 10 f c16 10 f c18 10 f c20 10 f c4 0. 1 f c13 0. 1 f c15 0. 1 f c17 0. 1 f c17 0. 1 f dg nd c19 0. 1 f c2 0. 1 f c1 0. 1 f c10 0. 1 f + + c5 10 f c6 0. 1 f + tp 1 o/p a v dd v ss u7 c22 1. 8pf j6 7 4 3 2 6 v? v+ + c25 10 f c23 10 f c26 0. 1 f c24 0. 1 f + tp 4 tp 3 tp 2 o/p b v dd r fb b v dd +v in v out trim gn d u1 ad5547 u6- a lk1 u2 2 5 3 4 1 v dd 1 a b ag nd 23 21 i out b 24 r fb a 3 i out a 2 v re f b v re f a j5 j2 ext re f b ext re f a 22 4 1 17 18 1 3 1 4 2 2 2 1 2 0 1 9 2 3 2 4 1 5 1 6 5 6 1 2 1 1 1 0 9 8 7 2 1 3 4 b 5 b 4 o e a b l e a b b 0 b 1 b 2 b 3 c e b a b 7 b 6 a 2 a 3 g n d c e a b a 7 a 6 a 5 a 4 o e b a l e b a a 0 a 1 5 6 1 2 1 1 1 0 9 8 7 2 1 3 4 b 5 b 4 o e a b l e a b b 0 b 1 b 2 b 3 c e b a b 7 b 6 a 2 a 3 g n d c e a b a 7 a 6 a 5 a 4 o e b a l e b a a 0 a 1 3 1 2 a 0 a 1 v cc v cc v c c v cc v c c p 1 ? 3 1 p 1 ? 1 p 1 ? 8 p 1 ? 9 p 1 ? 3 6 p 1 ? 1 4 p 1 ? 7 p 1 ? 6 p 1 ? 5 p 1 ? 4 p 1 ? 3 p 1 ? 2 j 4 j 3 u5 u4 74abt543 74a bt543 1 7 1 8 1 3 1 4 2 2 2 1 1 1 1 2 9 1 0 5 4 7 6 2 0 1 9 2 3 2 4 1 5 1 6 d b 0 1 8 d b 1 1 7 d b 7 1 1 d b 8 1 0 d b 9 9 d b 1 0 8 d b 1 1 7 c s 1 9 r w 2 0 6 d b 6 1 2 d b 5 1 3 d b 4 1 4 d b 3 1 5 d b 2 1 6 5 d g n d d g n d d g n d d b 0 d b 1 d b 7 d b 8 d b 9 d b 1 0 d b 1 1 c s r / w d a c _ a / b d b 6 d b 5 d b 4 d b 3 d b 2 e y 3 y 2 y 1 y 0 u6- b 1 3 1 5 1 4 a 0 a 1 e y 3 y 2 y 1 y 0 p1 ?19 p1 ?20 p1 ?21 p1 ?22 p1 ?23 p1 ?24 p1 ?25 p1 ?26 p1 ?27 p1 ?28 p1 ?29 p1 ?30 p 2 ? 3 p 2 ? 2 p 2 ? 1 p 2 ? 4 a g n d v ss v dd 1 v dd + p 2 ? 6 p 2 ? 5 + + + v cc f i gur e 4 5 . schem a t i c o f ad542 8/ ad544 0/ ad54 47 e v a l u a ti o n boa r d
ad5428/ad5440/ad 5447 rev. 0 | page 23 of 28 04462-0-036 f i g u re 46. co mpon ent - side a r t w ork 04462-0-038 f i gure 47. si lks c ree n c om pon e nt-si d e vie w ( t op laye r )
ad5428/ad5440/ad 5447 rev. 0 | page 24 of 28 04462-0-039 f i gure 48. s o ld er -si d e a r t w o r k
ad5428/ad5440/ad5447 rev. 0 | page 25 of 28 bill of materials table 12. name part description value tolerance (%) stock code c1 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c2 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c3 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c4 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c5 tantalum capacitortaj series 10 uf 10 v 10 fec 197-130 c6 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c7 npo ceramic capacitor 1.8 pf 10 fec 721-876 c8 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c9 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c10 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c11 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c12 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c13 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c14 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c15 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c16 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c17 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c18 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c19 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c20 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c21 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c22 npo ceramic capacitor 1.8 pf 10 fec 721-876 c23 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c24 x7r ceramic capacitor 0.1 uf 10 fec 499-675 c25 tantalum capacitortaj series 10 uf 20 v 10 fec 197-427 c26 x7r ceramic capacitor 0.1 uf 10 fec 499-675 cs, db0-11 red testpoint fec 240-345 (pack) j1-6 smb socket fec 310-682 j2 smb socket fec 310-682 j3 smb socket fec 310-682 j4 smb socket fec 310-682 j5 smb socket fec 310-682 j6 smb socket fec 310-682 lk1 3-pin header (2x2) fec 511-791&528-456 p1 36-pin centronics connector fec 147-753 p2 6-pin terminal block fec 151-792 rw red testpoint fec 240-345 (pack) tp1 to 4 red testpoint fec 240-345 (pack) u1 ad5428/ad5440/ad5447 ad5428yru / ad5440yru / ad5447yru u2 adr01 adr01ar u3 ad8065 ad8065ar u4, u5 74abt543 fairchild 74abt543cmtc u6 74139 cd74hct139m u7 ad8065 ad8065ar each corner rubber stick-on feet fec 148-922
ad5428/ad5440/ad5447 rev. 0 | page 26 of 28 overview of ad54xx devices table 13. part no. resolution no. dacs inl (lsb) interface package features ad5424 8 1 0.25 parallel ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-8 10 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru-24 10 mhz bw, 58 mhz serial ad5445 12 2 1 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial rj-8, rm-8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm-8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru-38 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru-38 4 mhz bw, 20 ns wr pulse width
ad5428/ad5440/ad 5447 rev. 0 | page 27 of 28 outline dimensions 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10 f i gure 49. 20-l ead t ssop (ru - 20) di me nsio ns sho w n i n mi ll im e t e r s 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153ad f i gure 50. 24-l ead t ssop (ru - 24) di me nsio ns sho w n i n mi ll im e t e r s
ad5428/ad5440/ad 5447 rev. 0 | page 28 of 28 ordering guide model resolution inl (lsbs) temperature range package descri ption package option ad5428yru 8 0.5 C40 c to +125c tssop (t hin shr i nk small outline package) ru-20 ad5428yru-re el 8 0.5 C40 c to +125c tssop (thin shr i nk small outline package) ru-20 ad5428yru-re el7 8 0.5 C40 c to +125c tsso p (thin shr i nk small outline package) ru-20 ad5440yru 10 0.5 C40 c to +125c tssop (t hin shr i nk small outline package) ru-24 ad5440yru-re el 10 0.5 C40 c to +125c tssop (thin shr i nk small outline package) ru-24 ad5440yru-re el7 10 0.5 C40 c to +125c tsso p (thin shr i nk small outline package) ru-24 ad5447yru 12 1 C40 c to +125c tssop (t hin shr i nk small outline package) ru-24 ad5447yru-re el 12 1 C40 c to +125c tssop (thin shr i nk small outline package) ru-24 ad5447yru-re el7 12 1 C40 c to +125c tssop (thin shr i nk small outline package) ru-24 eval-ad5428 e b e v a l u a t i o n k i t eval-ad5440 e b e v a l u a t i o n k i t eval-ad5447 e b e v a l u a t i o n k i t ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04462C0C 7/04(0)

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